Improved latch-up immunity in junction-isolated smart power ICs with unbiased guard ring

Author

Gupta, Sandhya ; Beckman, J.C. ; Kosier, S.L.

Author_Institution

PolarFab, Bloomington, MN, USA

Volume

22

Issue

12

fYear

2001

Firstpage

600

Lastpage

602

Abstract

The performance of the unbiased guard ring structure is measured and the effects of high current, emitter area, and layout of unbiased guard rings are reported and explained. Measurements show a reduction in parasitic gain by up to six orders of magnitude, while also avoiding the cross talk and power consumption of biased rings. A comparative analysis of unbiased guard ring with biased guard ring shows up to 100 times better performance at low current levels. A modification to the unbiased guard ring is also implemented and successfully tested which shows an increase in the current handling capability of the structure by an order of magnitude.

Keywords

MOS analogue integrated circuits; crosstalk; integrated circuit layout; integrated circuit testing; isolation technology; power integrated circuits; crosstalk isolation; current handling capability; emitter area; high current; high voltage LDMOS; junction-isolated smart power ICs; latch-up immunity; layout view; low-voltage CMOS control circuit; parasitic gain; unbiased guard ring; Area measurement; Current measurement; Energy consumption; Gain measurement; Immune system; Isolation technology; Performance analysis; Power integrated circuits; Power measurement; Protection;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.974591

Filename

974591