Title :
Efficient CMOS counter circuits
Author_Institution :
LSI Design Centre, IFM, Linkoping Univ.
fDate :
10/13/1988 12:00:00 AM
Abstract :
Several efficient counters are presented. A nine-transistor divide-by-two circuit is used as a basic building block. With transistor sizing, an input frequency of 400 MHz can be adopted by an asynchronous counter, while an eight-bit synchronous counter can achieve clock rates of more than 200 MHz in a 3-μm CMOS process. The power consumption of the proposed precharged dynamic synchronous counter is reduced to almost half as much as normal
Keywords :
CMOS integrated circuits; counting circuits; CMOS counter circuits; CMOS process; asynchronous counter; basic building block; clock rates; divide-by-two circuit; input frequency; power consumption; precharged dynamic synchronous counter; transistor sizing;
Journal_Title :
Electronics Letters
