Impact of gate direct tunneling current on circuit performance: a simulation study

Author

Choi, Chang-Hoon ; Nam, Ki-Young ; Yu, Zhiping ; Dutton, Robert W.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

Volume

48

Issue

12

fYear

2001

fDate

12/1/2001 12:00:00 AM

Firstpage

2823

Lastpage

2829

Abstract

The influence of gate direct tunneling current on ultrathin gate oxide MOS (1.1 nm⩽t_ox⩽1.5 nm, L_g=50-70 nm) circuits has been studied based on detailed simulations. For the gate oxide thickness down to 1.1 nm, gate direct tunneling currents, including the edge direct tunneling (EDT), show only a minor impact on low V_dd static-logic circuits. However, dynamic logic and analog circuits are more significantly influenced by the off-state leakage current for oxide thickness below 1.5 nm, under low-voltage operation. Based on the study, the oxide thicknesses which ensure the International Technological Roadmap for Semiconductors (ITRS) gate leakage limit are outlined both for high-performance and low-power devices

Keywords

CMOS analogue integrated circuits; CMOS logic circuits; circuit simulation; integrated circuit modelling; leakage currents; low-power electronics; tunnelling; 1.1 to 1.5 nm; 1.5 V; International Technological Roadmap for Semiconductors; analog circuits; circuit simulation; dynamic logic circuits; edge direct tunneling; gate direct tunneling current; gate leakage limit; gate oxide thickness; high-performance devices; low-voltage operation; off-state leakage current; static-logic circuits; ultrathin gate oxide CMOS circuits; CMOS logic circuits; CMOS technology; Circuit optimization; Circuit simulation; Leakage current; Logic circuits; Logic devices; MOSFET circuits; Semiconductor device modeling; Tunneling;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.974710

Filename

974710