Title :
A loadless CMOS four-transistor SRAM cell in a 0.18-μm logic technology
Author :
Noda, Kenji ; Matsui, Koujirou ; Takeda, Koichi ; Nakamura, Noritsugu
Author_Institution :
ULSI Device Dev. Div, NEC Corp., Kanagawa, Japan
fDate :
12/1/2001 12:00:00 AM
Abstract :
This paper presents a loadless CMOS four-transistor (4T) cell for very high density embedded SRAM applications. Using 0.18-μm CMOS technology, the memory cell size is 1.9344 μm2 (1.04 μm×1.86 μm), which is 35% smaller than a six-transistor (6T) cell using the same design rule. The newly developed CMOS 4T-SRAM cell operates with high stability at 1.8 V, even though its designed cell ratio is 1.0 to minimize the area. A pair of pMOS transfer transistors is used to store and retain full-swing signals in the cell without a refresh cycle. The fabrication process is fully compatible with high-performance CMOS logic technologies, because there is no need to integrate a poly-Si resistor or a TFT load
Keywords :
CMOS memory circuits; SRAM chips; circuit stability; embedded systems; integrated circuit design; integrated circuit noise; 0.18 micron; 0.18-μm logic technology; 1.8 V; cell ratio; full-swing signals; high stability; high-performance CMOS logic technologies; loadless CMOS four-transistor SRAM cell; memory cell size; pMOS transfer transistors; static-noise-margin; very high density embedded SRAM; CMOS logic circuits; CMOS process; CMOS technology; Fabrication; National electric code; Paper technology; Random access memory; Stability; Threshold voltage; Ultra large scale integration;
Journal_Title :
Electron Devices, IEEE Transactions on
