A Cyclic Vernier TDC for ADPLLs Synthesized From a Standard Cell Library

Author

Park, Youngmin ; Wentzloff, David D.

Author_Institution

Univ. of Michigan, Ann Arbor, MI, USA

Volume

58

Issue

7

fYear

2011

fDate

7/1/2011 12:00:00 AM

Firstpage

1511

Lastpage

1517

Abstract

This paper presents a cyclic Vernier time-to-digital converter (TDC) with digitally controlled oscillators (DCOs), targeted for a synthesizable all-digital phase locked loop (ADPLL). All functional blocks in the TDC are implemented with digital standard cells and placed-and-routed (P&R) by automatic design tools; thus, the TDC is portable and scalable to other process technologies. The effect of P&R mismatch is characterized in calibration mode, and utilized to achieve a minimum TDC resolution of 5.5 ps. The TDC was fabricated in a 65 nm CMOS process, and occupies 0.006 mm².

Keywords

CMOS digital integrated circuits; digital phase locked loops; network synthesis; ADPLL; CMOS process; cyclic Vernier TDC; digitally controlled oscillators; size 65 nm; standard cell library; synthesizable all-digital phase locked loop; time-to-digital converter; Calibration; Computer architecture; Image edge detection; Layout; Libraries; Microprocessors; Time measurement; All-digital PLL (ADPLL); Vernier; standard cell library; synthesis; time-to-digital converter (TDC);

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2011.2158490

Filename

5892913