Compact threshold-voltage model for short-channel partially-depleted (PD) SOI dynamic-threshold MOS (DTMOS) devices

Author

Kuo, James B. ; Yuan, Kuo-Hua ; Lin, Shih-Chia

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

Volume

49

Issue

1

fYear

2002

fDate

1/1/2002 12:00:00 AM

Firstpage

190

Lastpage

196

Abstract

This paper presents a closed-form threshold-voltage model for short-channel partially-depleted (PD) SOI dynamic-threshold MOS (DTMOS) devices based on a quasi-two-dimensional (2-D) approach. As verified by experimental data and 2-D simulation results, this compact model provides an accurate prediction of the threshold-voltage behavior of the short-channel PD SOI DTMOS devices. Based on the analytical model, as verified by the 2-D simulation results, PD SOI DTMOS devices have less short-channel effects including DIBL-induced short-channel effects as compared to the devices without the DTMOS configuration

Keywords

MOSFET; semiconductor device models; silicon-on-insulator; simulation; 2D simulation; DIBL-induced short-channel effects; DTMOS device; Si; analytical model; closed-form model; compact threshold voltage model; drain-induced-barrier lowering; dynamic-threshold MOS devices; partially-depleted SOI MOS devices; quasi-two-dimensional approach; short-channel SOI MOS devices; threshold-voltage behavior; Analytical models; Capacitance; Inductors; Microelectronics; Microwave devices; Microwave theory and techniques; Predictive models; Silicon; Solid state circuits; Substrates;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.974770

Filename

974770