Title :
Split-path skewed (SPS) CMOS buffer for high performance and low power applications
Author :
Hamzaoglu, Fatih ; Stan, Mircea R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA, USA
fDate :
10/1/2001 12:00:00 AM
Abstract :
Splitting a regular multistage CMOS buffer into two separate paths, and then skewing each path in opposite directions to achieve faster delay leads to a new, high-speed, split-path skewed (SPS) CMOS buffer. The two skewed paths are statically merged in the final stage such that the short-circuit current is eliminated without tri-stating the output. The proposed circuit is simulated for various skew values in a 0.18 μm CMOS technology for a 1.8 V supply voltage. The SPICE simulation results validate the fast operation of the proposed buffer and show that the energy delay product is always reduced and, for a skew value of four, the delay with respect to a regular tapered buffer design is reduced by 28% to 34%
Keywords :
CMOS digital integrated circuits; buffer circuits; cascade networks; delays; driver circuits; high-speed integrated circuits; low-power electronics; CMOS buffer; I/O driver; cascaded buffer design; fast operation; high performance applications; high-speed buffer; low power applications; split-path skewed buffer; CMOS technology; Capacitance; Circuit simulation; Clocks; Driver circuits; Energy consumption; Inverters; Logic devices; Power dissipation; Propagation delay;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on