Title :
Analytical thermal model for multilevel VLSI interconnects incorporating via effect
Author :
Chiang, Ting-Yen ; Banerjee, Kaustav ; Saraswat, Krishna C.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
The authors present compact analytical thermal models for estimating the temperature rise of multilevel VLSI interconnect lines incorporating via effect. The impact of vias has been modeled using (1) a characteristic thermal length and (2) an effective thermal conductivity of ILD (interlayer dielectric), k/sub ILD,eff/, with k/sub ILD/,/sub eff/=k/sub ILD//spl eta//, where /spl eta/ is a physical correction factor, with 0\n\n\t\t
Keywords :
VLSI; integrated circuit interconnections; integrated circuit modelling; temperature distribution; thermal analysis; thermal conductivity; Joule heating; characteristic thermal length; compact analytical thermal models; densely packed multilevel interconnects; effective thermal conductivity; heat dissipation; interlayer dielectric; low-k dielectrics; multilevel VLSI interconnect lines; multilevel interconnect arrays; spatial temperature profile; temperature rise estimation; via density; via effect; wire temperature distribution; Analytical models; Dielectrics; Heat sinks; Integrated circuit interconnections; Temperature distribution; Thermal conductivity; Thermal factors; Thermal resistance; Very large scale integration; Wire;
Journal_Title :
Electron Device Letters, IEEE
