DocumentCode :
1558039
Title :
A framework for reconfigurable computing: task scheduling and context management
Author :
Maestre, Rafael ; Kurdahi, Fadi J. ; Fernández, Milagros ; Hermida, Roman ; Bagherzadeh, Nader ; Singh, Hartej
Author_Institution :
Departamento de Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
Volume :
9
Issue :
6
fYear :
2001
Firstpage :
858
Lastpage :
873
Abstract :
Dynamically reconfigurable architectures are emerging as a viable design alternative to implement a wide range of computationally intensive applications. At the same time, an urgent necessity has arisen for support tool development to automate the design process and achieve optimal exploitation of the architectural features of the system. Task scheduling and context (configuration) management become very critical issues in achieving the high performance that digital signal processing (DSP) and multimedia applications demand. This article proposes a strategy to automate the design process which considers all possible optimizations that can be carried out at compilation time, regarding context and data transfers. This strategy is general in nature and could be applied to different reconfigurable systems. We also discuss the key aspects of the scheduling problem in a reconfigurable architecture such as MorphoSys. In particular, we focus on a task scheduling methodology for DSP and multimedia applications, as well as the context management and scheduling optimizations.
Keywords :
data flow graphs; high level synthesis; logic partitioning; processor scheduling; program compilers; reconfigurable architectures; reduced instruction set computing; CAD framework; DSP applications; MorphoSys; RISC processor; clustering; coarse grain reconfigurable system; code generator; configuration management; context management; data flow graph; design process automation; dynamically reconfigurable architectures; executable code; exploration algorithm; high-level input description; information extraction; kernel scheduler; multimedia applications; optimal exploitation; partitioning; performance tradeoffs; reconfigurable computing framework; reconfiguration time; support tool development; task scheduling; Application specific integrated circuits; Computer applications; Concurrent computing; Design optimization; Digital signal processing; Hardware; Optimization methods; Process design; Processor scheduling; Reconfigurable architectures;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/92.974899
Filename :
974899
Link To Document :
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