• DocumentCode
    1558054
  • Title

    A differential equation for placement analysis

  • Author

    Christie, Phillip

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Delaware Univ., Newark, DE, USA
  • Volume
    9
  • Issue
    6
  • fYear
    2001
  • Firstpage
    913
  • Lastpage
    921
  • Abstract
    A first-order differential equation for placement analysis is derived by considering the competing processes that generate and terminate wires crossing a circuit partition. The solution of this equation provides an estimate for the number of wires needed by a circuit partition for external communication and corresponds to the information normally associated with Rent´s rule. The rate model is shown to account not only for the simple power-law form of Rent´s rule for small partition sizes but also for deviations from power-law behavior observed for larger partition sizes. The accuracy of the model is validated by comparing solutions of the differential equation with experimental data extracted from a variety of netlists. The netlists, ranging from 10000 to 68000 cells, were optimized using a commercial placement tool. The accurate modeling of terminal-cell data results in a more robust predictive model for the distribution of wire lengths. This improved model accurately captures the change in the distribution of wires as the level of circuit placement optimization ranges from random to highly optimized placement. In addition, the new model provides an explanation for the experimentally observed inflection point and local maximum in the wire length distribution of some netlists.
  • Keywords
    VLSI; circuit optimisation; differential equations; logic arrays; logic partitioning; Rent´s rule; boundary-crossing wires; circuit partition; critical path; distribution of wires; external communication; first-order differential equation; gate array; gigascale integration design; improved model; optimized netlists; placement analysis; rate model; simple power-law form; terminal-cell data; two-terminal net placement; Data mining; Differential equations; Displays; Inspection; Predictive models; Printed circuits; Robustness; Terminology; Very large scale integration; Wires;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/92.974904
  • Filename
    974904