Title :
Exploiting the on-chip inductance in high-speed clock distribution networks
Author :
Ismail, Yehea I. ; Friedman, Eby G. ; Neves, Jose L.
Author_Institution :
Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Abstract :
On-chip inductance effects can be used to improve the performance of high-speed integrated circuits. Specifically, inductance improves the signal slew rate (the rise time), virtually eliminates short-circuit power consumption and reduces the area of the active devices and repeaters inserted to optimize the performance of long interconnects. These positive effects suggest the development of design strategies that benefit from on-chip inductance. An example of a clock distribution network is presented to illustrate the process in which inductance can be used to improve the performance of high-speed integrated circuits.
Keywords :
CMOS digital integrated circuits; high-speed integrated circuits; inductance; integrated circuit design; integrated circuit interconnections; power consumption; radio repeaters; CMOS; RLC; clock distribution network; high-speed integrated circuits; long interconnects; on-chip inductance effects; rise time; short-circuit power consumption; signal slew rate; Clocks; Energy consumption; High speed integrated circuits; Inductance; Integrated circuit interconnections; Integrated circuit noise; Intelligent networks; Network-on-a-chip; RLC circuits; Repeaters;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
