DocumentCode :
1558249
Title :
Optimum partitioning problem for rectilinear VLSI layout
Author :
Ku, L.-P. ; Leong, H.W.
Author_Institution :
Dept. of Inf. Syst. & Comput. Sci., Nat. Univ. of Singapore, Singapore
Volume :
144
Issue :
3
fYear :
1997
fDate :
5/1/1997 12:00:00 AM
Firstpage :
155
Lastpage :
162
Abstract :
The authors consider the optimum partitioning problem defined as follows: given a rectilinear layout L consisting of n rectangles, it is desirable to partition (decompose) the remaining free space into rectangular free blocks using horizontal and/or vertical partition edges such that the number of free blocks is minimised. The authors give a new formula for counting the number of free blocks in any partition of a given layout. Based on the new formula, they show that the optimum partitioning problem reduces to the problem of finding a maximum independent vertex set (MIS) in a bipartite graph. They then give an O(n 2.5) optimum partitioning algorithm (OPA) for computing an optimum partition. This optimum partitioning algorithm can be used to improve the space and time complexities of many applications where space partitioning is encountered. One example is the corner stitching data structure used for design rule checker (DRC) in the layout system Magic. In the experiments, the space complexity of the corner stitching data structure can be improved by an average of 13% by using the proposed optimum partitioning. Other applications are also presented
Keywords :
VLSI; circuit layout CAD; computational complexity; bipartite graph; corner stitching data structure; design rule checker; free blocks; free space; layout system Magic; maximum independent vertex set; optimum partitioning problem; rectilinear VLSI layout; space complexities; time complexities;
fLanguage :
English
Journal_Title :
Computers and Digital Techniques, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2387
Type :
jour
DOI :
10.1049/ip-cdt:19971158
Filename :
624311
Link To Document :
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