Bit error rate testing scheme for digital communication devices

In the present era, digital transmission of data plays a vital role in every sector. The main aim of this paper is to design a cost effective device which can test a transmission data and find the errors if any at the receiving end. Products based on this concept, having customizable options are widely available but with high cost. Most of the options in the testing equipment are unused, so there has been a requirement of a customized IP based tester with V.35 and PCM E1 framer which can serve in testing MODEMS. The 32 bit microcontroller STM32 monitors all the blocks on the testing board. The peripherals are connected to STM32 using various interfaces. The pattern generated is modulated on the transmission side of E1 framer or V.35. The MODEM receives the pattern and loops back it to the receiver section of E1 framer or V.35. Here the pattern is recovered via demodulator and passed to the BERT (Bit Error Rate Tester). If both are same then there will be no Bit Error, otherwise status register and bit error register values get updated automatically indicating the possibility of the error. The number of patterns generated by BERT is 23 and can be connected with multiple modems to test their working corresponding to different patterns. This process ensures the communication between MODEMS and BERT in a safest mode.