DocumentCode
1559303
Title
Limits on interconnection network performance
Author
Agarwal, Anant
Author_Institution
Lab. for Comput. Sci., MIT, Cambridge, MA, USA
Volume
2
Issue
4
fYear
1991
fDate
10/1/1991 12:00:00 AM
Firstpage
398
Lastpage
412
Abstract
The latency of direct networks is modeled, taking into account both switch and wire delays. A simple closed-form expression for contention in buffered, direct networks is derived and found to agree closely with simulations. The model includes the effects of packet size and communication locality. Network analysis under various constraints and under different workload parameters reveals that performance is highly sensitive to these constraints and workloads. A two-dimensional network is shown to have the lowest latency only when switch delays and network contention are ignored; three- or four-dimensional networks are favored otherwise. If communication locality exists, two-dimensional networks regain their advantage. Communication locality decreases both the base network latency and the network bandwidth requirements of applications. It is shown that a much larger fraction of the resulting performance improvement arises from the reduction in bandwidth requirements than from the decrease in latency
Keywords
multiprocessor interconnection networks; performance evaluation; buffered networks; closed-form expression; communication locality; direct networks; four-dimensional networks; interconnection network performance; latency; network bandwidth requirements; network contention; packet size; switch delays; two-dimensional network; wire delays; Bandwidth; Communication switching; Concurrent computing; Delay; Multiprocessing systems; Multiprocessor interconnection networks; Parallel processing; Performance analysis; Switches; Wire;
fLanguage
English
Journal_Title
Parallel and Distributed Systems, IEEE Transactions on
Publisher
ieee
ISSN
1045-9219
Type
jour
DOI
10.1109/71.97897
Filename
97897
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