High-speed and reduced-area modular adder structures for RNS

Author

Hiasat, Ahmed A.

Author_Institution

Electron. Eng. Dept., Princess Sumaya Univ. for Technol., Amman, Jordan

Volume

51

Issue

1

fYear

2002

fDate

1/1/2002 12:00:00 AM

Firstpage

84

Lastpage

89

Abstract

A modular adder is a very instrumental arithmetic component in implementing online residue-based computations for many digital signal processing applications. It is also a basic component in realizing modular multipliers and residue to binary converters. Thus, the design of a high-speed and reduced-area modular adder is an important issue. In this paper, we introduce a new modular adder design. It is based on utilizing concepts developed to realize binary-based adders. VLSI layout implementations and comparative analysis showed that the hardware requirements and the time delay of the new proposed structure are significantly, less than other reported ones. A new modulo (2ⁿ+1) adder is also presented. Compared with other similar ones, this specific modular adder requires less area and time delay

Keywords

adders; delays; digital arithmetic; residue number systems; VLSI layout implementations; carry-lookahead adder; digital signal processing; instrumental arithmetic component; modular multipliers; online residue-based computations; reduced-area modular adder structures; residue number system; residue to binary converters; terms-computer arithmetic; time delay; Adders; Delay effects; Digital arithmetic; Digital signal processing; Hardware; Instruments; Very large scale integration;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.980018

Filename

980018