• DocumentCode
    1559511
  • Title

    A new hardware architecture for operations in GF(2n)

  • Author

    Kim, Chang Han ; Oh, Sangho ; Lim, Jongin

  • Author_Institution
    Dept. of Computer-Aided Math. Inf. Sci., Semyung Univ., Chungbuk, South Korea
  • Volume
    51
  • Issue
    1
  • fYear
    2002
  • fDate
    1/1/2002 12:00:00 AM
  • Firstpage
    90
  • Lastpage
    92
  • Abstract
    The efficient computation of the arithmetic operations in finite fields is closely related to the particular ways in which the field elements are presented. The common field representations are a polynomial basis representation and a normal basis representation. In this paper, we introduce a nonconventional basis and present a new bit-parallel multiplier which is as efficient as the modified Massey-Omura multiplier using the type I optimal normal basis
  • Keywords
    digital arithmetic; multiplying circuits; polynomials; public key cryptography; arithmetic operations; bit-parallel multiplier; common field representations; finite fields; hardware architecture; modified Massey-Omura multiplier; normal basis representation; polynomial basis representation; public-key cryptosystems; type I optimal normal basis; Hardware;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.980019
  • Filename
    980019
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1559511