Title :
Simultaneous switching noise analysis and low-bounce buffer design
Author :
Jou, S.-J. ; Cheng, W.-C. ; Lin, Y.-T.
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
fDate :
12/1/2001 12:00:00 AM
Abstract :
An accurate equation to estimate simultaneous switching noise (SSN) created by CMOS output buffers is proposed. This analytic equation includes the carrier velocity saturation effects of a short-channel MOS transistor. Simulation results show that the proposed closed-form equation estimates the SSN precisely and the error is below 10% as compared with HSPICE simulation results. Design procedures of a low-bounce tapered buffer which take SSN into consideration are also proposed. Several output buffer design examples are demonstrated to show the significant improvement of the low-bounce buffer design. A test chip of the output buffer is implemented to operate at 400 MHz and the measurement results match the design specifications
Keywords :
CMOS digital integrated circuits; buffer circuits; delay estimation; high-speed integrated circuits; integrated circuit design; integrated circuit noise; 400 MHz; CMOS output buffers; SSN effects; alpha-power law model; carrier velocity saturation effects; closed-form equation; delay time estimation; low-bounce buffer design; short-channel MOS transistor; short-channel MOSFET; simultaneous switching noise analysis; tapered buffer;
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings -
DOI :
10.1049/ip-cds:20010624
