DocumentCode :
1559708
Title :
Impact of 0.25 μm dual gate oxide thickness CMOS process on flicker noise performance of multifingered deep-submicron MOS devices
Author :
Chew, K.W. ; Yeo, K.S. ; Chu, S.-F. ; Wang, Y.M.
Author_Institution :
Chartered Semicond. Manuf. Ltd, Singapore, Singapore
Volume :
148
Issue :
6
fYear :
2001
fDate :
12/1/2001 12:00:00 AM
Firstpage :
312
Lastpage :
317
Abstract :
The flicker noise performance of 0.25 μm thin gate oxide transistors from the dual gate oxide thickness process and the single gate oxide thickness process have been evaluated and compared. A total of 20 transistors have been measured. The results reveal that thin gate oxide transistors from the dual gate oxide thickness process show a maximum of an order reduction in the current noise spectra. This reduction can be attributed to the lower nitrogen concentration peak at the Si/SiO2 interface. Hence the dual gate oxide thickness process will be the state-of-the-art for the implementation of system-on-chip designs. In general, the low-frequency noise behaviour of the fabricated deep-submicrometre MOSFETs is best described by the number fluctuation with the correlated mobility fluctuation model
Keywords :
1/f noise; CMOS integrated circuits; carrier mobility; flicker noise; fluctuations; integrated circuit noise; interface states; semiconductor-insulator boundaries; silicon; 0.25 micron; LF noise behaviour; N; N concentration peak; Si-SiO2; Si/SiO2 interface; correlated mobility fluctuation model; current noise spectra reduction; deep-submicron CMOS devices; dual gate oxide thickness CMOS process; flicker noise performance; low-frequency noise behaviour; multifingered CMOS devices; single gate oxide thickness process; system-on-chip designs;
fLanguage :
English
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2409
Type :
jour
DOI :
10.1049/ip-cds:20010626
Filename :
980768
Link To Document :
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