Title :
Ultralow resistance W/poly-Si gate CMOS technology using amorphous-Si/TiN buffer layer
Author :
Wakabayashi, Hitoshi ; Yamamoto, Toyoji ; Yoshida, Kazuyoshi ; Soda, Eiichi ; Tokunaga, Ken-Ichi ; Mogami, Tohru ; Kunio, Takemitsu
Author_Institution :
Silicon Syst. Res. Labs., NEC Corp., Kanagawa, Japan
fDate :
2/1/2002 12:00:00 AM
Abstract :
Advanced tungsten/pn-poly-Si gate CMOS devices with an ultralow sheet resistance of 1 Ω/sq. have been demonstrated using an amorphous-Si/TiN buffer layer. A low-resistivity tungsten film is formed by large grain size tungsten on an amorphous-silicon (a-Si) film. This result can be explained by the Mayadas-Shatzkes theory. After a source/drain annealing process, W/a-Si/TiN/pn-poly-Si systems become W/WSix/TiN/pn-poly-Si systems without impurity interdiffusion between the pn-poly-Si gate electrodes. The propagation delay time of a CMOS inverter ring oscillator with this novel gate electrode is considerably smaller than that with a cobalt-salicide film in a wider channel width
Keywords :
CMOS integrated circuits; amorphous semiconductors; annealing; chemical interdiffusion; delays; diffusion barriers; electric resistance; elemental semiconductors; grain size; integrated circuit measurement; integrated circuit metallisation; oscillators; silicon; titanium compounds; tungsten; CMOS inverter ring oscillator; Mayadas-Shatzkes theory; W-Si-TiN-Si; W-WSi-TiN-Si; W/WSix/TiN/pn-poly-Si systems; W/a-Si/TiN/pn-poly-Si systems; a-Si film; amorphous-Si/TiN buffer layer; amorphous-silicon film; channel width; gate electrode; impurity interdiffusion; low-resistivity tungsten film; pn-poly-Si gate electrodes; propagation delay time; sheet resistance; source/drain annealing process; tungsten grain size; tungsten/pn-poly-Si gate CMOS devices; ultralow resistance W/poly-Si gate CMOS technology; Annealing; Buffer layers; CMOS technology; Electrodes; Grain size; Impurities; Inverters; Propagation delay; Tin; Tungsten;
Journal_Title :
Electron Devices, IEEE Transactions on
