Title :
Threshold voltage roll-up/roll-off characteristic control in sub-0.2-μm single workfunction gate CMOS for high-performance DRAM applications
Author :
Inaba, Satoshi ; Katsumata, Ryota ; Akatsu, Hiroyuki ; Rengarajan, Rajesh ; Ronsheim, Paul ; Murthy, Cheruvu S. ; Sunouchi, Kazumasa ; Bronner, Gary B.
Author_Institution :
Toshiba-IBM R&D Center, Toshiba America Electron. Components Inc., Hopewell Junction, NY, USA
fDate :
2/1/2002 12:00:00 AM
Abstract :
Threshold voltage (Vt) roll-off/roll-up control is a key issue to achieve high-performance sub-0.2-μm single workfunction gate CMOS devices for high-speed DRAM applications. It is experimentally confirmed that a combination of well RTA and N2 implant prior to gate oxidation is important to reduce Vt roll-up characteristics both in nFET and pFET. Optimization of RTA conditions after source/drain (S/D) implant is also discussed as a means of improving Vt roll-off characteristics. Finally, the impact of halo implant on Vt variation in sub-0.2-μm buried channel pFETs is discussed. It is found that halo profile control is necessary for tight Vt variation in sub-0.2-μm single workfunction gate pFET
Keywords :
CMOS memory circuits; DRAM chips; buried layers; doping profiles; high-speed integrated circuits; ion implantation; oxidation; rapid thermal annealing; work function; 0.2 micron; N2 implant; RTA conditions optimization; buried channel pFETs; gate oxidation; halo implant; halo profile control; halo structure; high-performance DRAM applications; high-speed DRAM applications; single workfunction gate CMOS; single workfunction gate CMOS devices; single workfunction gate pFET; source/drain implant; threshold voltage roll-off; threshold voltage roll-up; threshold voltage roll-up/roll-off characteristic control; well RTA; CMOS process; CMOS technology; Implants; Impurities; Minimization; Oxidation; Random access memory; Research and development; Threshold voltage; Voltage control;
Journal_Title :
Electron Devices, IEEE Transactions on
