DocumentCode
1559841
Title
A capacitor-less 1T-DRAM cell
Author
Okhonin, S. ; Nagoga, M. ; Sallese, J.M. ; Fazan, P.
Author_Institution
Signal Process. Lab., LEG, Lausanne, Switzerland
Volume
23
Issue
2
fYear
2002
Firstpage
85
Lastpage
87
Abstract
A simple true 1 transistor dynamic random access memory (DRAM) cell concept is proposed for the first time, using the body charging of partially-depleted SOI devices to store the logic "1" or "0" binary states. This cell is two times smaller in area than the conventional 8F/sup 2/ 1T/1C DRAM cell and the process of its manufacturing does not require the storage capacitor fabrication steps. This concept will allow the manufacture of simple low cost DRAM and embedded DRAM chips for 100 and sub-100 nm generations.
Keywords
CMOS memory circuits; DRAM chips; impact ionisation; silicon-on-insulator; CMOS scales; DRAM; SOI MOSFET; body charging; capacitor-less cell; eDRAM; embedded chips; floating body effects; impact ionization; partially-depleted SOI devices; simple low cost manufacture; single transistor cell concept; CMOS technology; Capacitors; Electrical resistance measurement; Fabrication; Leg; MOSFET circuits; Manufacturing; Random access memory; Time measurement; Writing;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.981314
Filename
981314
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