Title :
A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme
Author :
Sim, Jae-Yoon ; Nam, Jang-Jin ; Sohn, Young-Soo ; Park, Hong-June ; Kim, Chang-Hyun ; Cho, Soo-In
Author_Institution :
Dept. of Electr. Eng., Pohang Univ. of Sci. & Technol., Kyungbuk, South Korea
fDate :
2/1/2002 12:00:00 AM
Abstract :
An equalizing transceiver was implemented by using a 0.35-μm CMOS technology for DRAM bus system. An equalization scheme was used in the receiver to reduce intersymbol interference (ISI). To maximize the data rate, a one-to-eight demultiplexing scheme was used in the equalizer of the receiver such that eight equalizers operate in parallel at the clock frequency, which is one-eighth the data rate. The maximum data rates were measured to be 840 Mb/s with twelve 5-pF capacitors connected in uniform spacing along a transmission line. The test criterion for successive transmission was set to the bit-error rate (BER) of 10-12 for the pseudorandom binary sequence (PRBS) data. The effectiveness of equalizers was demonstrated by measuring the BER with equalizers on and off, respectively. The chip size was 800×400 μm2 and the supply voltage was 3.3 V
Keywords :
CMOS analogue integrated circuits; analogue processing circuits; demultiplexing; equalisers; feedforward; high-pass filters; high-speed integrated circuits; intersymbol interference; storage management chips; transceivers; 0.35 micron; 3.3 V; 840 Mbit/s; CMOS transceiver; DRAM bus system; bit-error rate; clock frequency; demultiplexed equalization scheme; intersymbol interference; maximum data rates; one-to-eight demultiplexing scheme; pseudorandom binary sequence; supply voltage; Bit error rate; CMOS technology; Clocks; Demultiplexing; Equalizers; Frequency; Intersymbol interference; Random access memory; Transceivers; Transmission line measurements;
Journal_Title :
Solid-State Circuits, IEEE Journal of
