A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs

Author

Wee, Jae-Kyung ; Min, Kyeong-Sik ; Park, Jong-Tai ; Lee, Sang-Pil ; Kim, Young-Hee ; Yang, Tae-Heum ; Joo, Jong-Doo ; Chung, Jin-Yong

Author_Institution

Memory R&D Div., Hynix Semicond. Inc., Kyoungki, South Korea

Volume

37

Issue

2

fYear

2002

fDate

2/1/2002 12:00:00 AM

Firstpage

251

Lastpage

254

Abstract

A bipolar-voltage programmable antifuse circuit scheme and bit-repair scheme are newly proposed for post package repair. For fail-bit repair, the antifuses in the proposed scheme are programmed by bipolar voltages of V_CC and -V_CC, alleviating high-voltage problems such as permanent device breakdown and achieving a smaller layout area for the antifuse circuit than the previous scheme. In addition, an efficient bit-repair scheme is used instead of the conventional line-repair scheme, reducing the layout area for the redundancy bits. Also, using static latches instead of dynamic memory cells for the redundancy bits eliminates possible defects in the redundancy area, making this bit-repair scheme robust and avoiding burn-in stress issues. Through manufacturing commercial DRAM products, the yield improvement by the one-bit post-package repair reaches as much as 2.4% for 0.16-μm triple-well 256-M SDRAM

Keywords

DRAM chips; MOS capacitors; integrated circuit layout; integrated circuit packaging; integrated circuit yield; maintenance engineering; programmable circuits; redundancy; 0.16 micron; 256 Mbit; MOS capacitors; antifuse EPROM structure; antifuse circuit layout area; bipolar programming voltage scheme; bipolar-voltage programmable antifuse circuit; commercial DRAM products; fail-bit repair; high-density DRAMs; post-package bit-repair scheme; redundancy bits; static latches; three-stage Dickson charge-pump circuit; triple-well 256-M SDRAM; yield improvement; Breakdown voltage; Charge pumps; Circuits; Latches; MOS capacitors; Packaging; Random access memory; Redundancy; Robustness; Stress;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.982432

Filename

982432