Title :
An architecture and implementation of MPEG audio layer III decoder using dual-core DSP
Author :
Lee, Kyu Ha ; Lee, Keun-Sup ; Hwang, Tae-Hoon ; Park, Young-Cheol ; Youn, Dae Hee
Author_Institution :
Samsung Thales Co. Ltd., Kyungki-Do, South Korea
fDate :
11/1/2001 12:00:00 AM
Abstract :
A new architecture for the MP3 decoding system is proposed and implemented. The proposed system is based on a processor employing a dual-core (DSP and RISC) architecture. The MP3 decoding algorithm is implemented using the DSP core with high accuracy, and the RISC core performs bitstream buffering and system control in conjunction with a user interface. The system with this configuration can support an efficient parallel processing between DSP and RISC cores, so that it is possible to minimize the computational overhead. The implemented system employs a flash memory card for the storage, and it has a file management system that is compatible with PC. Also, it supports all sampling rates and data rates specified in MPEG-1/2 standards. The MP3 decoder developed is suitable for portable communication devices such as cellular telephones since it features high audio quality, low-power consumption and cost effectiveness
Keywords :
audio coding; cellular radio; code standards; decoding; digital signal processing chips; file organisation; flash memories; memory cards; parallel architectures; reduced instruction set computing; MP3 decoding; MPEG audio layer III; MPEG-1/2 standards; PC; RISC; audio quality; bit-stream buffering; cellular telephones; cost effectiveness; data rates; decoder; dual-core DSP; dual-core architecture; file management system; flash memory card; parallel processing; power consumption; sampling rates; system control; user interface; Concurrent computing; Control systems; Decoding; Digital audio players; Digital signal processing; Flash memory; Parallel processing; Reduced instruction set computing; Sampling methods; User interfaces;
Journal_Title :
Consumer Electronics, IEEE Transactions on
