Characterization of current-mode CMOS R-2R ladder digital-to-analog converters

Author

Wang, Lei ; Fukatsu, Yasunori ; Watanabe, Kenzo

Author_Institution

Res. Inst. of Electron., Shizuoka Univ., Hamamatsu, Japan

Volume

50

Issue

6

fYear

2001

fDate

12/1/2001 12:00:00 AM

Firstpage

1781

Lastpage

1786

Abstract

A digital-to-analog (D/A) converter based on the R-2R ladder is first analyzed in terms of the power consumption, to point out that the current-mode is the lowest power dissipation counterpart of the voltage-mode. The integral nonlinearity (INL) analyses and the characterization methods of the current-mode D/A converter are then presented to identify the error sources. The methods are applied to an 8-bit D/A converter fabricated using a 0.6 μm CMOS process. Measured results compared with INL analyses indicate that the dominant error source of a prototype converter is the resistance of the metal interconnect between the ladder and the bonding pad, and the INL of the ladder itself is 1.2 LSB

Keywords

CMOS integrated circuits; current-mode circuits; digital-analogue conversion; errors; integrated circuit measurement; low-power electronics; network analysis; 0.6 micron; 8 bit; CMOS process; D/A converter; INL analysis; R-2R ladder; characterization methods; current-mode DAC; digital-to-analog converter; error sources; integral nonlinearity; low power operation; metal interconnect resistance; power consumption; resistive ladder; CMOS process; CMOS technology; Digital-analog conversion; Electrical resistance measurement; Energy consumption; Power dissipation; Resistors; Switches; Switching converters; Voltage;

fLanguage

English

Journal_Title

Instrumentation and Measurement, IEEE Transactions on

Publisher

ieee

ISSN

0018-9456

Type

jour

DOI

10.1109/19.982980

Filename

982980