• DocumentCode
    1560596
  • Title

    A cost-effective 2-D discrete cosine transform processor with reconfigurable datapath

  • Author

    Lai, Yeong-Kang ; Hsu, Hun-Jen

  • Author_Institution
    Dept. of Electr. Eng., Nat. Chung-Hsing Univ., Taichung, Taiwan
  • Volume
    2
  • fYear
    2003
  • Abstract
    In this paper, a cost-effective 2D discrete cosine transform processor using a reconfigurable datapath is described. The proposed architecture uses some multiplexers to reduce computational complexity. This processor operates on 8×8 blocks. Unlike other direct methods, the proposed architecture is regular for VLSI implementation. The proposed 2D DCT processor costs 38598 transistors, with an operating frequency of 100 MHz, using 0.35 μm CMOS technology.
  • Keywords
    CMOS logic circuits; VLSI; discrete cosine transforms; integrated circuit design; logic design; reconfigurable architectures; 0.35 micron; 100 MHz; 2D discrete cosine transform processor; CMOS; VLSI implementation; computational complexity reduction; cost-effective DCT processor; multiplexers; processor operating block size; reconfigurable datapath processor; CMOS technology; Costs; Discrete Fourier transforms; Discrete cosine transforms; Fourier transforms; Hardware; Matrix decomposition; Multiplexing; Transform coding; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
  • Print_ISBN
    0-7803-7761-3
  • Type

    conf

  • DOI
    10.1109/ISCAS.2003.1206018
  • Filename
    1206018
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1560596