A system-on-chip featuring variable bus architecture and enhanced video coprocessors for MPEG-4 multimedia applications

Author

Jeon, MinYong ; Byun, Hyunll ; Ha, JooHo ; KiTaek Lee ; Kim, JooHyoung ; Seo, JiYoung ; Lee, KiTaek ; Lee, SeungHo

Author_Institution

Semicond. Lab., C & S Technol., Inc, Seoul, South Korea

Volume

2

fYear

2003

Abstract

A media processor supporting MPEG-4 SP@L3 and H.263 baseline has been eveloped. This chip includes a RISC core, dedicated video accelerator, audio/voice CODEC, pre/post processor, and some peripherals. In order to increase flexibility and reduce power dissipation, a configurable bus architecture that may optimize the bus transaction overhead was adopted. Not only dedicated coprocessors for the acceleration of multimedia processing but also some novel techniques such as zero vector skip, DCT reduction, and localized isolation of functional blocks were implemented for the application specific performance tuning. Enhanced error resilience was also implemented for error-prone environment, and additional innovative low-power design techniques were applied for portable applications. This processor contains 2M gates on 56mm² die using of 0.18um CMOS HLM technology.

Keywords

CMOS digital integrated circuits; coprocessors; low-power electronics; multimedia communication; reconfigurable architectures; system buses; system-on-chip; video codecs; 0.18 micron; CMOS HLM technology; H.263; MPEG-4 SP@L3; MPEG-4 multimedia codec processor; configurable bus architecture; error resilience; low-power design; system-on-chip; video coprocessor; Acceleration; CMOS technology; Codecs; Coprocessors; Discrete cosine transforms; MPEG 4 Standard; Multimedia systems; Power dissipation; Reduced instruction set computing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1206090

Filename

1206090