C-V test structures for metal gate CMOS

Author

Bankras, Radko G. ; Tiggelman, Mark P J ; Negara, M. Adi ; Sasse, Guido T. ; Schmitz, Jurriaan

Author_Institution

MESA+ Inst. for Nanotechnol., Twente Univ., Enschede, Netherlands

fYear

2006

Firstpage

226

Lastpage

229

Abstract

Gate leakage has complicated the layout and measurement of C-V test structures. In this paper the impact of metal gate introduction to C-V test structure design is discussed. The metal gate allows for wider-gate structures and for the application of n⁺-^p- diffusion edges. We show, both theoretically and with experimental data, the impact of both design modifications on C-V measurement results.

Keywords

CMOS integrated circuits; capacitance measurement; voltage measurement; C-V test structure design; C-V test structure measurement; capacitance-voltage test structure layout; gate leakage; metal gate CMOS; CMOS technology; Capacitance-voltage characteristics; Contact resistance; Electrical resistance measurement; Equations; Fingers; Frequency measurement; Gate leakage; MOSFETs; Semiconductor device testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2006. ICMTS 2006. IEEE International Conference on

Print_ISBN

1-4244-0167-4

Type

conf

DOI

10.1109/ICMTS.2006.1614309

Filename

1614309

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1560920