DocumentCode
1561129
Title
A negative-overhead, self-timed pipeline
Author
Winters, Brian D. ; Greenstreet, Mark R.
Author_Institution
Department of Computer Science, University of British Columbia, BC, Canada
fYear
2002
Firstpage
37
Lastpage
46
Abstract
This paper presents a novel variation of wave pipelining that we call "surfing." In previous wave pipelined designs, timing uncertainty grows monotonically as events propagate through gates or other logic elements. We bound this dispersion by propagating a timing pulse along with the data values. Our logic elements have delays that are smaller in the presence of the pulse than in its absence. This produces a "surfing" effect: events are bound in close proximity to the timing pulse. We demonstrate this approach with the design of a 4 × 12 multiplier. Spice simulations from the extracted layout indicate that this design is robust in the presence of fabrication parameter variation and power supply noise. Because timing is maintained by accelerating the logic, our designs achieve lower latency than their purely combinational equivalents. Thus, the control overhead for these designs is indeed negative.
Keywords
SPICE; delays; integrated circuit noise; logic simulation; multiplying circuits; pipeline processing; timing; Spice simulations; delays; fabrication parameter variation; latency; logic elements; multiplier; negative-overhead self-timed pipeline; power supply noise; surfing; timing pulse; timing uncertainty; wave pipelining; Delay; Fabrication; Logic design; Logic gates; Noise robustness; Pipeline processing; Power supplies; Pulsed power supplies; Timing; Uncertainty;
fLanguage
English
Publisher
ieee
Conference_Titel
Asynchronous Circuits and Systems, 2002. Proceedings. Eighth International Symposium on
ISSN
1522-8681
Print_ISBN
0-7695-1540-1
Type
conf
DOI
10.1109/ASYNC.2002.1000294
Filename
1000294
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