Title :
Checking delay-insensitivity: 104 gates and beyond
Author :
Kondratyev, Alex ; Neukom, Lawrence ; Roig, Oriol ; Taubin, Alexander ; Fant, Karl
Abstract :
Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verifying circuits whose behavior is independent of component delays (delay-insensitive). It shows that for a particular way of implementing a delay-insensitive circuit, through a Null Convention Logic methodology, the complexity of the verification task might be significantly reduced. This method is implemented using Satisfiability (SAT) solvers and is successfully tested on realistic design examples having tens of thousands of gates.
Keywords :
asynchronous circuits; circuit analysis computing; combinational circuits; computability; formal verification; integrated logic circuits; Boolean networks; NCL circuits; combinational circuit; component delay independence; convention logic methodology; delay-insensitive circuits; delay-insensitive encoding; delay-insensitivity analysis; satisfiability solvers; verification task complexity reduction; Asynchronous circuits; Automatic control; Clocks; Delay effects; Design automation; Laboratories; Logic circuits; Protocols; Timing; Wire;
Conference_Titel :
Asynchronous Circuits and Systems, 2002. Proceedings. Eighth International Symposium on
Print_ISBN :
0-7695-1540-1
DOI :
10.1109/ASYNC.2002.1000305
