Adding synchronous and LSSD modes to asynchronous circuits

Author

Van Berkel, Kees ; Peeters, Ad ; Te Beest, Frank

Author_Institution

Philips Res. Labs., Eindhoven, Netherlands

fYear

2002

Firstpage

161

Lastpage

170

Abstract

A synchronous mode as well as a scan mode of operation are added to a large class of asynchronous circuits, in compliance with LSSD design rules. This enables the application of mainstream tools for design-for-testability and test-pattern generation to asynchronous circuits. The approach is based on a systematic transformation of all single-output sequential gates into synchronous and scannable versions. By exploiting dynamic circuit operation in scan mode, the overhead of this transformation in terms of both circuit cost and circuit delay is kept minimal.

Keywords

CMOS logic circuits; asynchronous circuits; design for testability; logic design; CMOS gates; LSSD design rules compliance; LSSD mode; asynchronous circuits; design-for-testability; dynamic circuit operation; scan mode; scannable versions; sequential gates transformation; single-output sequential gates; synchronous mode; synchronous versions; test pattern generation; Asynchronous circuits; Circuit testing; Clocks; Combinational circuits; Delay; Latches; Logic; Multiplexing; Reflection; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Asynchronous Circuits and Systems, 2002. Proceedings. Eighth International Symposium on

ISSN

1522-8681

Print_ISBN

0-7695-1540-1

Type

conf

DOI

10.1109/ASYNC.2002.1000306

Filename

1000306