DocumentCode
1561224
Title
Testing of asynchronous designs by "inappropriate" means. Synchronous approach
Author
Kondratyev, Alex ; Sorensen, Lief ; Streich, Amy
Author_Institution
Cadence Berkeley Lab., CA, USA
fYear
2002
Firstpage
171
Lastpage
180
Abstract
The roadblock to wide acceptance of asynchronous methodology is poor CAD support. Current asynchronous design tools require a significant re-education of designers, and their capabilities are far behind synchronous commercial tools. This paper considers the testing methodology for a particular subclass of asynchronous circuits (Null Convention Logic or NCL) that entirely relies on conventional CAD tools available at today\´s market. It is shown that for acyclic NCL pipelines a test pattern generation for stuck-at faults could be effectively solved through the construction and checking of the synchronous circuit with a set of faults "equivalent" to the original NCL circuit. This result is extended to arbitrary NCL structures by applying the partial scan technique to break computational loops. The method guarantees 100% stuck-at fault coverage in NCL systems, which is confirmed by experimental data.
Keywords
asynchronous circuits; automatic test pattern generation; combinational circuits; fault diagnosis; integrated circuit testing; integrated logic circuits; logic testing; ATPG; CAD tools; acyclic NCL pipelines; asynchronous circuits; asynchronous design; convention logic; partial scan technique; stuck-at faults; synchronous approach; synchronous circuit checking; test pattern generation; testing methodology; Asynchronous circuits; Circuit faults; Circuit simulation; Circuit synthesis; Circuit testing; Design automation; Laboratories; Logic circuits; Logic design; Logic testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Asynchronous Circuits and Systems, 2002. Proceedings. Eighth International Symposium on
ISSN
1522-8681
Print_ISBN
0-7695-1540-1
Type
conf
DOI
10.1109/ASYNC.2002.1000307
Filename
1000307
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