Power integrity/signal integrity co-simulation for fast design closure

There is a growing need to reduce the design cycle time of electronic packages to meet the consumer needs quicker. A design methodology to achieve this is to integrate signal and power-delivery analysis. In this paper, a transient simulation technique using S-parameters that does not violate causality is presented. Eye-diagram results are shown, with and without explicit delay extraction. Scalability of this technique has been demonstrated by solving a large sized problem