Title :
An accurate behavioral model of phase detectors for clock recovery circuits
Author :
Balsi, M. ; Centurelli, F. ; Scotti, G. ; Tommasino, P. ; Trifiletti, A.
Author_Institution :
Dipt. di Ingegneria Elettronica, Univ. di Roma, Italy
Abstract :
We propose in this paper a behavioral modeling technique of analog phase detectors for clock recovery applications, that allows fast but accurate simulations of PLL and clock recovery systems. The model is extracted from transistor-level simulations of the phase detector circuit, thus it can be used for behavioral simulations of the PLL in the design verification phase of a systematic design methodology. The technique is applied to a DRML phase detector for 2.5 Gb/s applications in Si BJT technology (27 GHz fT), providing a rms error below 5%.
Keywords :
bipolar analogue integrated circuits; circuit simulation; integrated circuit modelling; jitter; phase detectors; phase locked loops; synchronisation; 2.5 Gbit/s; 27 GHz; DRML phase detector; PLL; Si BJT technology; analog phase detectors; behavioral model; clock recovery circuits; design verification phase; fast accurate simulations; jitter behavior; rms error; systematic design methodology; transistor-level simulations; Circuit simulation; Clocks; Design methodology; Digital communication; Jitter; Low pass filters; Phase detection; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206175
