An accurate behavioral model of phase detectors for clock recovery circuits

We propose in this paper a behavioral modeling technique of analog phase detectors for clock recovery applications, that allows fast but accurate simulations of PLL and clock recovery systems. The model is extracted from transistor-level simulations of the phase detector circuit, thus it can be used for behavioral simulations of the PLL in the design verification phase of a systematic design methodology. The technique is applied to a DRML phase detector for 2.5 Gb/s applications in Si BJT technology (27 GHz f_T), providing a rms error below 5%.