Wafer level processing on re-built wafer for chip stacking

Chip stacking has emerged as the best solution to reduce the packaging size (Karnezos, 2004). Several approaches are proposed by companies and laboratories and each of them presents specific advantages and drawbacks (Tummala, 2004). Today, major 3D applications are stacked memory DRAM, SRAM or flash. Moreover, cost acts as a brake on 3D expansion in SiP and further developments are necessary to reduce the packaging cost. One clearly identified way is to perform collective processes. New developments on wafer level packaging and 3D packaging are lead in a European project (called Walpack) (Poupon, 2004; Souriau, 2005) to fulfil the requirement of the company 3D-PLUS. The proposed technology aims to realise 3D modules, as 3D-PLUS already produces, but using ultra thin components inside. To realise such module, the original approach consist in reconstituting a wafer with the active sides aligned in the same plane, embedded in a resin which gives the wafer its mechanical consistency. The known good re-built chips are then stacked and 3D interconnected by means of the patented 3D-PLUS process