Field programmable gate arrays and analog implementation of BRIN for optimization problems

The binary relation inference network (BRIN) emerges as a powerful topological network to solve various constrained optimization problems. In this paper, the BRIN solution is reviewed for the sake of reference. The analog and digital realization of BRIN is presented. For the analog implementation, we studied the BRIN solution for the transitive closure problem. We used commonly available integrated circuits and general minimum and maximum building blocks. The network response was discussed. The worst solution time for a general path problem was estimated. For a digital implementation of the BRIN solution, field programmable gates arrays (FPGA) with millions of gates, were studied with Xilinx´s system generator. The detailed implementation is presented. The network response and the solution time are analyzed and the comparisons between both platforms are discussed.