Parametric design and solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

Wafer level packaging (WLP) has many advantages, such as ease of fabrication and reduced fabrication cost. However, solder joint reliability of traditional WLPs is the weakest point of the technology. In this paper, a 0.4mm pitch Cu post type WLP has been developed for mobile computing. The Cu post type WLP has 440 I/Os and 12 times 12 mm die size. The initial design WLP has been fabricated and experienced a thermal cycling (TC) testing. The initial failure life of the original WLP under TC is only 296 cycles. This paper also presents a nonlinear finite element analysis on the board level solder joint reliability enhancement of the WLP. A viscoplastic constitutive relation is adopted for the solders to account for its time and temperature dependence in TC. The fatigue life of solder joint is estimated by the modified Coffin-Manson equation. The two coefficients in the modified Coffin-Manson equation are also determined. A series of parametric study is performed by changing the passivation (PI) thickness, redistribution layer (RDL) thickness, polymer height (Cu post height accordingly), die thickness, PCB thickness, and PCB CTE. The results obtained from the modeling are useful to form design guidelines for board level reliability enhancement of the WLP