Table look-up based compact modeling for on-chip interconnect timing and noise analysis

A compact model for RLC interconnect lines, in the form of a two-path hybrid ladder, is proposed for on-chip interconnect timing and noise analysis. The model parameters are synthesized through constrained nonlinear optimization to directly match the circuit response characteristics over a range of transition times and loads, both at the driving point and at the receiver end. The effect of capacitances on the return current distribution is explicitly considered in our work in obtaining the accurate responses for industrial circuits, and is found to have a significant effect. The parameters for this model are embedded in a table that is characterized once for a design and then used for the analysis of various structured interconnects. Compared with a prior compact modeling approach, our model is demonstrated to accurately predict responses such as the interconnect delay, gate delay, transition times at near and far ends of switching lines as well as the overshoot at the far ends of switching lines.