DocumentCode :
1561442
Title :
New dynamic logic-level converters for high performance application
Author :
Kim, Nom-Seog ; Yoon, Yong-Jin ; Cho, Uk-Rae ; Byun, Hyun-Geun
Author_Institution :
SRAM Design, Memory Div., Samsung Electron., South Korea
Volume :
5
fYear :
2003
Abstract :
Two new logic-level converting circuits are presented for high performance application. One of them is the dynamic logic-level converter (DLC). It has fast transition time in converting the logic-level, and its power consumption is smaller than that of conventional approaches. The other is a dynamic logic-level converter for duty ratio conserving (DDLC). The duty ratio or cycle of a level converted signal generated by the DDLC is equal to that of an input signal. The devices are applied to a 72 Mb DDR SRAM. The DLC and the DDLC allow the core of the chip to operate at a lower voltage level (1.2 V) than the I/O supply voltage level (1.5 V or 1.8 V). In this application, transition time of the DLC is less than 120 psec, and the duty cycle for signal converted by the DDLC are higher than that of an input signal by 1.1%. The area overhead in the chip is 0.03%.
Keywords :
SRAM chips; convertors; integrated logic circuits; low-power electronics; 1.2 V; 72 Mbit; DDLC; DDR SRAM; DLC; duty cycle; duty ratio conservation; dynamic logic-level converter; low-voltage operation; power consumption; transition time; CMOS logic circuits; CMOS technology; Delay; Energy consumption; MOSFET circuits; Pulse power systems; Random access memory; Switches; Switching converters; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
Type :
conf
DOI :
10.1109/ISCAS.2003.1206195
Filename :
1206195
Link To Document :
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