• DocumentCode
    1561470
  • Title

    Area-efficient memory-based architecture for FFT processing

  • Author

    Moon, Sang-Chul ; Park, In-Cheol

  • Author_Institution
    Dept. of EECS, KAIST, Daejeon, South Korea
  • Volume
    5
  • fYear
    2003
  • Abstract
    In this paper, we propose a new area-efficient parallel architecture to calculate 2n-point FFT. The proposed architecture is based on the radix-4 Cooley-Tukey algorithm, and consists of four complex multipliers, eight complex adders, and four RAMs each of which is partitioned into two banks. The implemented FFT processor can calculate 2 K/4 K/8 K-point complex FFT in 28.2 μs/62.0 μs/135.2 μs at 91 MHz, respectively.
  • Keywords
    adders; digital arithmetic; fast Fourier transforms; logic design; parallel architectures; random-access storage; 135.2 mus; 28.2 mus; 2n-point FFT; 62.0 mus; 91 MHz; FFT area-efficient memory-based architecture; FFT processing speed; bank partitioned RAM; complex FFT processor; complex adders; complex multipliers; parallel architecture; radix-4 Cooley-Tukey algorithm; Computer architecture; Delay; Discrete Fourier transforms; Flexible printed circuits; Memory architecture; Moon; OFDM; Partitioning algorithms; Throughput; Wideband;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
  • Print_ISBN
    0-7803-7761-3
  • Type

    conf

  • DOI
    10.1109/ISCAS.2003.1206198
  • Filename
    1206198
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1561470