Predictive solder joint reliability assessment of board-on-chip package for DDR-II DRAM application

A solder joint life prediction process utilizing finite element modeling is described. The main target is the board-on-chip (BOC) package for the DDR-II DRAM. 3D finite element model is developed in a parametric and automatic manner to effectively investigate various design/material perspectives. The model is verified with real package deformation measured by a moire interferometric technique. Several available models for solder joint life prediction are carefully reviewed in the model. The predicted results from various models are verified with experimental thermal cycling test data. Also, studies have been conducted to predict the fatigue life of two solder materials (SnPb and SnAgCu) and pad designs (SMD and NSMD) as well as a number of package design/material parameters. The predicted results show a good agreement with the experimental thermal cycling data. The effects of package design, ball pad design, package mount layout, and solder material on solder joint life are also investigated