Title :
5 GHz pipelined multiplier and MAC in 0.18 μm complementary static CMOS
Author :
Sulistyo, J. ; Ha, D.
Author_Institution :
Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
Abstract :
Wave pipelining improves the throughput of a circuit by exploiting the delays of combinational elements, rather than register clocks, for synchronization. Our proposed approach, called HyPipe, combines conventional pipelining with wave pipelining and aims to take advantage of both pipelining methods. In this paper, we investigated 4-bit signed multipliers and 4-bit MACs based on the HyPipe approach. The circuits were implemented in fully complementary CMOS in TSMC 0.18 μm technology. Simulation results indicate that the two circuits can operate at 5 GHz at 1.8 V and 1.05 GHz at 0.8 V, which are far higher than previous results reported in the open literature.
Keywords :
CMOS logic circuits; high-speed integrated circuits; integrated circuit design; logic design; multiplying circuits; pipeline arithmetic; synchronisation; 0.18 micron; 0.8 V; 1.05 GHz; 1.8 V; 4 bit; 5 GHz; HyPipe; MACs; TSMC technology; conventional pipelining; full adder; fully complementary static CMOS; pipelined multiplier; pipelined multiplier and MAC; signed multipliers; synchronization; wave pipelining; Adders; Clocks; Combinational circuits; Logic; Pipeline processing; Propagation delay; Registers; Synchronization; Throughput; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206204
