DocumentCode :
1561533
Title :
A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder
Author :
Chow, Hwang-Chemg ; Wey, I-Chyn
Author_Institution :
Inst. of Semicond. Technol., Chang Gung Univ., Tao-Yuan, Taiwan
Volume :
5
fYear :
2003
Abstract :
In this paper, a high speed, low latency pipelined Booth multiplier with new Manchester carry-bypass adder (MCBA) is proposed. By using new partial product generation scheme and new MCBA, the latency is reduced to 6. By using new MCBA, the speed bottleneck is overcome with 40.16% improvement and the energy can be saved with 30.59% improvement. The 13-bit new MCBA pipelined into 2 stages can operate above 1 GHz with worst-case delay of 0.833 ns and consumed only 16.81 mW. Finally, the proposed pipelined Booth multiplier is presented at 3.3 V, 1 GHz in TSMC 0.35 μm process with a power consumption of only 60.18 mW.
Keywords :
CMOS logic circuits; adders; high-speed integrated circuits; multiplying circuits; pipeline arithmetic; 0.35 micron; 0.833 ns; 1 GHz; 13 bit; 16.81 mW; 3.3 V; 60.18 mW; Manchester carry-pass adder; TSMC CMOS process; high speed multiplier; low latency multiplier; partial product generation scheme; pipelined Booth multiplier; Algorithm design and analysis; Central Processing Unit; Decoding; Delay; Digital arithmetic; Digital signal processing; Digital signal processors; Digital systems; Encoding; Energy consumption;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
Type :
conf
DOI :
10.1109/ISCAS.2003.1206205
Filename :
1206205
Link To Document :
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