A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems

Author

Soudris, D. ; Sgouropoulos, K. ; Tatas, K. ; Pavlidis, V. ; Thanailakis, A.

Author_Institution

Dept. of Electr. & Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece

Volume

5

fYear

2003

Abstract

The goal of the research is twofold: first, the derivation of a design methodology for FIR filter implementation based on the Residue Number System (RNS), aiming at power, delay and hardware complexity reduction compared with conventional binary implementations. Second, a CAD tool development, which generates a synthesizable VHDL description of any RNS system design in an automatic way. This tool can derive RNS full adder-based DSP architectures consisting of FIR, scaling, converters, multiplication and accumulation units.

Keywords

FIR filters; VLSI; circuit CAD; digital filters; digital signal processing chips; integrated circuit design; logic CAD; residue number systems; CAD tool development; FIR filters; RNS full adder-based DSP architectures; RNS-based system design; accumulation units; delay reduction; design methodology; hardware complexity reduction; multiplication units; power reduction; residue number system; synthesizable VHDL description; Concurrent computing; Design automation; Design engineering; Design methodology; Digital signal processing; Energy consumption; Finite impulse response filter; Hardware; Read only memory; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1206208

Filename

1206208