A flexible LUT-based carry chain for FPGAs

In this paper we propose a new type of carry chain designed for FPGAs, which allows good performance with a limited area occupation dedicated to the chain. The main features of our chain are full uniformity in the bidimensional tile array, as well as the absence of constraints in the operand size and in the position of any logic resource. The flexibility of this chain is such that a wide class of functions can be mapped, differently from other existing solutions designed only for adders. This carry chain has worked properly on a test chip developed by using 0.18 μm CMOS STMicroelectronics technology.