DocumentCode
1561571
Title
Low-error fixed-width squarer design
Author
Cho, K.J. ; Choi, E.M. ; Chung, J.G. ; Lim, Myung Sub ; Kim, J.K.
Author_Institution
Dept. of Electron. & Inf. Eng., Chonbuk Nat. Univ., Chonju, South Korea
Volume
5
fYear
2003
Abstract
This paper presents a design method for fixed-width squarer that receives a W-bit input and produces a W-bit squared product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on quantization error. Then, different error compensation methods are applied to each group. By simulation, it is shown that the performance of the proposed method is pretty close to that of the rounding operation and much better than that of the truncation operation.
Keywords
digital arithmetic; error compensation; integrated circuit design; integrated logic circuits; logic design; quantisation (signal); Booth encoder outputs; Booth folding technique; error compensation bias; error compensation methods; fixed-width squarer; low-error squarer design; quantization error; Design methodology; Digital signal processing; Encoding; Equalizers; Error compensation; Error correction; Frequency domain analysis; Image coding; Image recognition; Vector quantization;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN
0-7803-7761-3
Type
conf
DOI
10.1109/ISCAS.2003.1206210
Filename
1206210
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