Title :
Area-time optimal adder with relative placement generator
Author :
Farooqui, Aamir A. ; Oklobdzija, Vojin G. ; Sait, Sadiq M.
Author_Institution :
Synopsys Module Compiler, Synopsys Inc., Mountain View, CA, USA
Abstract :
This paper presents design of an adder generator, for the production of area-time-optimal adders. A unique feature of the proposed generator is its integrated synthesis and layout environment achieved by providing relative placement information to the synthesis tool. Adders produced by this generator are dynamically configured for a given technology library, wire-load model, delay, and area goal. The adder architecture used in this generator is a hybrid of Brent and Kung (1982), carry select, and ripple carry adders. When compared with standard cell fast adders, a 20%-50% reduction in area with comparable delays is achieved. The reduction comes from a judicious selection of ripple carry or carry select adders based on computation of delays. When performance is being met, the carry select adders are replaced with ripple carry adders. The proposed generator has been integrated into a commercially available high-performance datapath design tool.
Keywords :
VLSI; adders; carry logic; circuit CAD; circuit layout CAD; circuit optimisation; delays; high level synthesis; integrated circuit layout; integrated logic circuits; adder generator design; area-time-optimal adders; carry select adders; delay; high-performance datapath design tool; integrated synthesis layout environment; relative placement generator; ripple carry adders; wire-load model; Adders; Costs; Delay; Hybrid power systems; Integrated circuit interconnections; Laboratories; Libraries; Minerals; Petroleum; Production;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206211
