Title :
Design of a self-timed asynchronous parallel FIR filter using CSCD
Author :
Lampinen, Harri ; Perälä, Pauli ; Vainio, Olli
Author_Institution :
Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland
Abstract :
This paper presents a self-timed, asynchronous, parallel finite impulse response (FIR) filter architecture capable of high-speed operation. Using self-timed, parallel structures even slow calculation blocks, such as simple multiplier-accumulators (MACs), can be used to implement high-speed filters. The building blocks are implemented using specific current-sensing completion detection (CSCD) standard cells also presented in this paper. The simulation results are very promising and especially the design of the control revealed several pitfalls and possibilities that require specific solutions when designing asynchronous circuits.
Keywords :
FIR filters; asynchronous circuits; cellular arrays; network synthesis; parallel architectures; current-sensing completion detection standard cell; high-speed circuit design; multiplier-accumulator; self-timed asynchronous parallel FIR filter architecture; Asynchronous circuits; Clocks; Delay; Electronic design automation and methodology; Finite impulse response filter; Logic circuits; Logic design; Pipeline processing; Protocols; Switches;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206219
