Automatic analog layout retargeting for new processes and device sizes

Author

Jangkrajarng, N. ; Bhattacharya, Sumbuddha ; Hartono, R. ; Shi, C. J Richard

Author_Institution

Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA

Volume

4

fYear

2003

Abstract

This paper presents an automatic analog layout resizing tool that can generate a new layout incorporating the target technology process and the target transistor sizes. The tool automatically preserves the analog layout integrity by extracting layout symmetry and matching, and then solving the constrained layout generation problem using a combined linear programming and graph-theoretic approach. The tool has been applied successfully to integrate specified transistor sizes and to migrate layouts for various analog designs from TSMC 0.25 μm CMOS to TSMC 0.18 μm CMOS process with comparable performances to re-design.

Keywords

CMOS analogue integrated circuits; circuit layout CAD; graph theory; integrated circuit layout; linear programming; operational amplifiers; 0.18 to 0.25 micron; TSMC CMOS process; analog layout integrity; automatic analog layout resizing tool; automatic analog layout retargeting; constrained layout generation problem; folded cascode operational amplifier; graph-theoretic approach; layout symmetry; linear programming; target technology process; target transistor sizes; two-stage operational amplifier; Analog circuits; CMOS process; CMOS technology; Compaction; Data mining; Digital circuits; Linear programming; Microprocessors; Transistors; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1206224

Filename

1206224