High-speed ADC using residue number system

An ADC (analog/digital converter) architecture based on a residue number system (RNS) and multiple folding of the input signal is described. The number of comparators used is equal to the sum of moduli for obtaining the dynamic range desired. An error correction circuit and overflow detection are possible. RNS ADC makes use of an analog preprocessing stage for multiple folding of the input signal before flash conversion to reduce the hardware and to achieve high-speed operation. The main drawback of the architecture is that a residue code that does not change gradually, such as the Gray code, and error correction are necessary to avoid large errors. Higher resolution is possible without much increase in hardware. It is concluded that this reduced hardware architecture results in a low-cost high-speed ADC suitable for consumer video applications